In general, the design of semiconductor integrated circuits follows a set method. To begin with, a schematic circuit, which is a diagram showing connections between circuit devices, can be designed by a schematic tool. Next, the respective circuit devices included in the schematic circuit can be designed by patterns of such material layers as a conductive layer, a semiconductor layer, and an insulation layer. Then, a layout is designed where the respective patterns are disposed in vertical and horizontal directions, and the respective material layers are repeatedly deposited and patterned based on the layout. Thus, a semiconductor integrated circuit having a desired function can be manufactured.
When a schematic circuit of a semiconductor integrated circuit is drawn by a schematic tool, a netlist extracted from the schematic tool is simulated using a simulation device to inspect the operation of the semiconductor integrated circuit. If the results of the simulation are not satisfactory, the schematic circuit is modified. Here, the netlist is a file extracted from the schematic tool. This netlist is used for simulation or for layout versus schematic (LVS) comparison after the design of the semiconductor integrated circuit has been completed. The netlist represents connections between circuit devices included in the schematic circuit as well as connections between functional blocks (i.e., cells) formed of the circuit devices.
Conventionally, during a pre-layout stage of the design of the semiconductor integrated circuit, a conventional device did not include a design unit for automatically connecting cells on a schematic circuit to generate interconnections (or wires). For this reason, a designer had to predict the path of the interconnection and then directly input a schematic circuit of the interconnection using a schematic editor of a schematic tool. Thus, the designer could model only a part of the parasitic resistance and the parasitic capacitance of the interconnection, which greatly affect the performance of the semiconductor integrated circuit. As a result, the work of designing the parasitic resistance and parasitic capacitance of the interconnection increases design costs and design time. Also, when a floor plan, which is schematic layout information of a semiconductor integrated circuit, was changed, it was difficult to change the parasitic resistance and parasitic capacitance of the interconnection. Therefore, in the pre-layout stage, it was difficult to perform a simulation on the semiconductor integrated circuit, considering the parasitic resistance and parasitic capacitance of the interconnection.
Further, in a post-layout step of a semiconductor integrated circuit, when the semiconductor integrated circuit was simulated, a netlist file of an interconnection including parasitic resistance and parasitic capacitance, extracted from a layout of the semiconductor integrated circuit, was directly interfaced in a simulation device. Thus, when the semiconductor integrated circuit was simulated, errors such as a convergence error occurred often. Also, a lot of problems were caused when a control card was input or a probe sentence was inserted for analysis of the simulation results. Also, connections needed to be inconveniently tracked from the netlist having file formats other than the schematic circuit during the analysis of the simulation results.
There is at present a layout design unit (e.g., a CAD tool), which automatically extracts the critical path of the designed semiconductor integrated circuit and then provides a simulation device with a netlist on the critical path. A designer designates an input port and an output port of the critical path. But, as the netlist input to the simulation device has a particular file format, if a schematic circuit is changed, the foregoing simulation method using the layout design unit may become inconvenient. Also, since the critical path is automatically extracted based on input information such as the input port and output port, the critical path considered by the designer may not be defined. Besides, the simulation method is applied to the full-chip of the semiconductor integrated circuit, and this may require a large simulation time.